b70-optimization-lab

Intel And vLLM Suggestions

This file collects the actionable feedback from the Qwen3.6 35B lane. The detailed upstream backlog lives in:

Hardware note for Intel/vLLM readers: these suggestions come from a four-B70 lab with 128 GB aggregate VRAM. That is enough to expose real XPU graph, MoE, KV, and driver issues, but it is not enough to test larger families with much headroom or to keep independent inference service and optimization lanes running at the same time. Access to higher-VRAM Intel evaluation hardware would turn several “future model” bullets into runnable repros.

Highest-Value vLLM/XPU Items

  1. Make XPU graph provenance explicit.
    • Graph-none, skipped-capture, and PIECEWISE forced-comm runs must be distinguishable in metrics and summaries.
    • Emit capture count, skipped-capture reasons, graph memory, and replay hit rate into the run summary.
  2. Add graph-safe verifier state hooks for speculative decode.
    • GDN/Mamba/SSM models need rollback and commit operations that are ordered with graph replay.
    • Eager copy_ state restore between captured decode replays is not robust.
  3. Improve XPU error diagnostics.
    • Device-lost, OOR, IGC error-code-245, and graph-capture failures need concise, actionable logs with the failing shape and kernel path.
    • Current failures often surface as generic engine-core cancellation after a worker dies.
  4. Continue upstream kernel-package bakeoffs.
    • XPU-native MoE, route GEMM, GDN/DFlash graph padding, B70 attention, KV fixes, and graph-safe collectives remain plausible baseline improvements.
  5. Treat B70 topology and runtime as first-class benchmark identity.
    • P2P checksums, network interface, oneCCL/OFI settings, driver/runtime versions, IGC version, and graph/collective flags need to be captured with every claim.

Intel Runtime Feedback

The repeated problems are not only model-level:

What To Port To Other Models