b70-optimization-lab

MiniMax Scheduler and XCCL Microbench Screens, 2026-05-10

Summary

After the Q/K apply+RoPE helper regressed compiled throughput, I screened two low-risk vLLM scheduling/compile settings and then measured raw XCCL allreduce latency at MiniMax decode tensor sizes.

Conclusion:

vLLM Screens

Baseline for p512/n512:

--no-async-scheduling:

Static compile size 1:

An earlier shorthand attempt with -cc.compile_sizes+ 1 failed before model load because pydantic received "1" as a string. Use compact JSON when retesting compilation config.

XCCL Microbenchmark

I extended benchmarks/b70_xccl_allreduce_bench.py to include MiniMax decode sizes:

Default oneCCL/XCCL:

CCL_TOPO_FABRIC_VERTEX_CONNECTION_CHECK=0:

CCL_SYCL_ALLREDUCE_TMP_BUF=1:

CCL_ALLREDUCE_SMALL_THRESHOLD=0:

CCL_ALLREDUCE=direct:

Interpretation

The raw default XCCL latency for MiniMax-sized allreduces is lower than the synchronized per-layer timing seen inside vLLM. That means the next useful work should not be more oneCCL environment toggles. Better targets:

Source for the oneCCL algorithm caveat: