b70-optimization-lab

2026-05-07 FP8 TP4 vs PP2xTP2 Refresh

Context

After reboot and the Q4_0 guard-fix validation, I refreshed the static FP8 path using vrfai/Qwen3.6-27B-FP8 with the local vLLM/XPU tree at c51df4300 plus the existing local XPU patches. The goal was to re-check the proposed 2x2 layout and compare it against the known TP4 speed path at the same 512 prompt / 512 output shape.

All runs used max_model_len=32768, QUANTIZATION=compressed-tensors, KV_CACHE_DTYPE=auto, XPU FlashAttention2, CCL_ATL_TRANSPORT=ofi, no power-limit changes, and the reusable scripts/bench-vllm-qwen36-fp8.sh wrapper.

Results

Layout Extra setting Speculative tok/s out tok/s total Avg latency
PP2xTP2 default CCL topology no 27.722318 55.444635 18.468874 s
TP4/PP1 default CCL topology no 45.864956 91.729913 11.163207 s
TP4/PP1 default CCL topology n-gram 4, lookup 2..4 48.082178 96.164356 10.648436 s
TP4/PP1 CCL_TOPO_FABRIC_VERTEX_CONNECTION_CHECK=0 no 46.386137 92.772274 11.037781 s
TP4/PP1 CCL_TOPO_FABRIC_VERTEX_CONNECTION_CHECK=0 n-gram 4, lookup 2..4 44.438715 88.877430 11.521485 s

Observations

LocalMaxxing

Submitted the PP2xTP2 capacity-focused negative result:

Artifacts